Integrated circuits produced by SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits generally induce lower parasitical capacitances, which make it possible to improve the switching speed. Moreover, the phenomenon of parasitic triggering (“latch-up”) encountered by MOS transistors in Bulk technology can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC or MEMS type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiation and therefore turn out to be more reliable in applications where such radiation may induce operational problems, in particular in space applications. SOI integrated circuits can be used for random-access memories of SRAM type or logic gates.
In a known manner, such integrated circuits also include devices for protecting against accidental electrostatic discharges (ESD) that can impair these transistors.
An ESD device observes certain technological restrictions. FIG. 1 is an example of a current-voltage diagram of an ESD device during a discharge. Upon the appearance of an electrostatic discharge, the voltage across the terminals of the ESD device first increases to a trigger voltage Vt1. The current passing through the ESD device therefore increases slightly (low leakage). This voltage Vt1 must remain below a voltage Vm, corresponding to a breakdown voltage in MOS technology, typically of 2.6 V for FDSOI with a technological node of 28 nm. The voltage Vt1 is also greater than a supply voltage Vdd of the various circuits in order to avoid accidental triggering of the ESD device. The voltage Vt1 is thus typically above a voltage of 1.1·Vdd.
When the triggering voltage Vt1 is reached, the ESD device is triggered. Firstly, the voltage across the terminals of the ESD device can decrease while the current passing through it continues to rise. Secondly, the voltage across the terminals of the ESD device increases, in the same way as the current passing through it in order to short-circuit the electrostatic discharge current. In this second step, the ESD device must have as low an on-resistance as possible, in order to exhibit as high a maximum short-circuit current It2 as possible for a voltage below the voltage Vm.
Moreover, the ESD device must generally have as low a leakage current as possible before being triggered. This reduces the electrical consumption of the integrated circuit.
ESD devices often occupy a non-negligible surface region of the integrated circuit, which it is desirable to minimize. Moreover, the fabrication process of an ESD device must entail a minimum of additional steps to avoid excessively increasing the cost of the integrated circuit.